Week at a Glance

Monday, November 1, 2010

Track 1 - ReSpace and Track 2 - MAPLD (Tutorial Session)

Afternoon Tutorial Session - 1

1:00 pm - 5:00 pm Hansen: Space Plug-and-Play Avionics (SPA) Overview (ITAR Restricted)

6:00 pm Reception

Afternoon Tutorial Session - 2

1:00 pm - 2:15 pm Villarreal: Riverside Optimizing Compiler For Configurable Computing (ROCC)

2:30 pm - 3:45 pm Zufelt: Mini PnP ITAR Free

4:00 pm - 5:15 pm Alexander: Failure Mechanisms Affecting Performance And Longevity Of Space Electronics

6:00 pm Reception

Afternoon Tutorial Session - 3

1:00 pm - 2:15 pm Dailey: Designing FPGAs For Space - Top Down, Bottom Up, Inside Out, Etc.

2:30 pm - 3:45 pm Berg: Optimizing Mitigation Strategies For FPGA Critical Applications

4:00 pm - 5:15 pm Smith: Can You Really Design FPGAs With System Verilog?

6:00 pm Reception

Evening Tutorial Sessions (No Registration Required)

7:30 pm until 9:00pm Swift: Rad 101 - Introduction To Radiation Effects On Electronics

7:30 pm until 9:00pm Vera: Partial Configuration

Tuesday, November 2, 2010

Plenary Session

7:00 am - 8:00 am Breakfast

8:00 am - 8:15 am Suddarth: Opening Remarks

8:15 am - 9:00 am Abbot: History Of Surrey

9:00 am - 9:45 am Puig-Suari: History Of Cube Sats

9:45 am - 10:15 am Break

10:15 am - 10:30 am Powell: NASA Opening Remarks

10:30 am - 11:00 am Fabula: Revolution of SIRF

11:00 am - 11:30 am Lyke: SPA Creative Concepts (with SPA-O)

11:30 am - 1:00 pm Lunch and Panel Session (Are You Crazy Flying That?)-Panel Moderator: Ken LaBel, NASA

Track 1 - ReSpace (SPA Standardization)

1:00 pm - 1:30 pm Howe: Kit Of Parts Architecture

1:30 pm - 2:000 pm
Hansen / Graven: GNC Hierarchy Using SPA

2:00 pm - 2:30 pm
Christensen / Cannon: SPA Network Management

2:30 pm - 3:00 pm Break

3:00 pm - 3:30 pm Schenk: Advanced Plug - n - Play Technologies (APT) Lessons Learned

3:30 pm - 5:00 pm Making SPA Work: Industry Input, the Standards Process, and Where we are Now - Panel Chair: Millay Morgan, APT

6:00 pm Dinner

Track 2 - MAPLD

Session A

1:00 pm - 1:10 pm
Ward: Non-Volatile And Volatile Carbon Nanotube Electronics For Reconfigurable, Radiation Hard Space Based Applications

1:10 pm - 1:20 pm
Wang: Very High Density and Radiation Tolerant PROM For Space Syatems

1:20 pm - 1:30 pm Philpy: Research Microsystems And The Coming Revolution In Space

1:30 pm - 1:40 pm Wolday: Actel's RTAX4000D Space Qualification Update

1:40 pm - 1:50 pm Katzman: Space Qualified Ultra-High Speed Plug-and Play Radiation Hard SERDES

1:50 pm - 2:00 pm Lake: Aeroflex Non-Volatile Boot Memory For Xilinx FPGAs

2:00 pm - 2:10 pm Swonger: Radiation Hardened Integrated Point-of-load DC-DC Converter On Sapphire

2:10 pm - 2:20 pm Puncher: High Speed Radiation Hard 72Mbit Quad Data Rate SRAM For Space Applications

2:20 pm - 2:30 pm Carmichael: Introducing The Virtex-5QV Reconfigurable FPGA: The Biggest And Fastest Space-grade Part On The Planet

2:30 pm - 3:00 pm Break

3:00 pm - 3:10 pm Ginosar: JPIC - Rad-Hard JPEG2000 Image Compression ASIC

3:10 pm - 3:20 pm Bancelin: ATMEL ATF280F Rad Hard SRAM Based Dynamic Partial Reconfiguration

3:20 pm - 3:30 pm Jones: The Advantages And Challenges Of Using Many-core Processors For Space-based Applications

3:30 pm - 3:40 pm Elftmann: RadRunner

Session B

3:40 pm - 4:00 pm Dupre: The Cibola Flight Experiment Payload: Flexible, Responsive, Space-Based Reconfigurable Computing

4:00 pm - 4:20 pm Petrick: Spacecube

4:20 pm - 4:40 pm Morgan: LANL Cube Sat Reconfigurable Computer (CRC)

4:40 pm - 5:00 pm Howard: Highly Scalable/Highly Configurable FPGA Based Solid State Recorder For Multi-Mission Space Applications

6:00 pm Dinner

Wednesday, November 3, 2010

Track 1 - ReSpace and Track 2 - MAPLD (Combined Session - Software Defined Radio)

7:30 am - 8:30 am Breakfast

8:30 am - 8:50 am Anthony: Development Of NASA’s Space Communications And Navigation Test Bed Aboard ISS To Investigate SDR, On-board Networking And Navigation Technologies

8:50 am - 9:10 am Palmer: The Firehouse Adaptive Software Defined Radio

9:10 am - 9:30 am Mast: Software Defined Payloads

9:30 am - 10:00 am Kief: COSMIAC Ground Station

10:00 am - 10:30 am Break

10:30 am - 10:50 am Sauer: Research And Development Of A Flexible Communication Platform For Space

10:50 am - 11:10 am Olivieri: Responsive Satellite Communications Via FPGA-Based Software-Defined Radio For SPA-U Compatible Platforms

10:10 am - 11:30 am Lynaugh: Software Defined Radio

11:30 am - 1:00 pm Lunch

Track 1 - ReSpace (New Architectures For Aerospace)

1:00 pm - 1:30 pm Phidget: Turning Vision Into Reality

1:30 pm - 2:00 pm Boesen: Integration Of The Self-Healing eDNA Architecture In An Embedded System And Evaluation Of A Fourier Transform Spectrometer Instrument Application

2:00 pm - 2:30 pm
Bruhn: Introducing A Low Cost and High Performing Interoperable Satellite Platform Based On Plug-and-Play Technology For Modular and Reconfigurable Civilian And Military Nanosatellites

2:30 pm - 3:00 pm Mee: Commercial Off-The-Shelf SPA1 ASIM

3:00 pm - 3:30 pm Break

3:30 pm - 4:00 pm Ardalan: On-demand On-line Scrubbing Of The RHBD Structured ASIC Appliqué Sensor Interface Module

4:00 pm - 4:30 pm Newman: Spacecraft Plug and Play Avionics Experiment - On Orbit Results – David Newman - SNC Space Systems

4:30 pm - 5:00 pm Eddy: AFRL's AI & T Tool Flow Software

5:00 pm - 5:30 pm McGuirk - LV SPA

6:30 pm Dinner

Track 2 - MAPLD

Session B contd...

1:00 pm - 1:20 pm
Bradley: Field Programmable Gate Array (FPGA)-Based Digital Signal Processor (DSP) For The NASA Soil Moisture Active Passive (SMAP) Radio-frequency Interference (RFI) Mitigating Radiometer

1:20 pm - 1:40 pm
Jones: HXiS: The HyperX Processor in Space

1:40 pm - 2:00 pm To Be Determined

Session C

2:00 pm - 2:20 pm Black: Impact Of Ion-Induced Meta-Stable Conditions On Clocked Operations Of DICE Flip-Flops For Reconfigurable Devices

2:20 pm - 2:40 pm Monson: Fault Injection Results Of Linux On An FPGA Embedded Platform

2:40 pm - 3:00 pm Bit-Accurate, At-Speed Hardware Verification For DO-254 Compliance

3:00 pm - 3:30 pm Break

3:30 pm - 3:50 pm McGuffey: A comparison of the effectiveness of SEE Mitigation On RTAX-S/SL And ProASIC3E FPGAs

3:50 pm - 4:10 pm Present And Future Of Space Design Verification

4:10 pm - 4:30 pm Abdallah: The Challenge Of Hold Time Check In Timing Critical FPGA Designs

4:30 pm - 4:50 pm Figueredo: Developing A Framework For Independent Validation And Verification Of Complex Space FPGAs For NASA Spacecrafte

6:30 pm Dinner

Thursday, November 4, 2010

Track 1 - ReSpace (On The Horizon)

7:30 am - 8:30 am Breakfast

8:30 am - 8:50 am Furano: CANopen Networks As An Enabler For Modern Space-Borne Control Systems: The European Space Agency’s Perspective

8:50 am - 9:10 am Vahid - Composing Video/Sensor-Based Automated Notification Systems Using Spatial Programming

9:10 am - 9:30 am Wender: Monolithic-MCM Analog IC Design For Space

9:30 am - 10:00 am Anderson: Psoc

10:00 am - 10:30 am Break

10:30 am - 10:50 am Rodrigue: Multiple Network Tiers Support Robust SPA Spacecraft

10:50 am - 11:10 am Pattichis: Adaptive Wiring Manifold

11:10 am - 11:30 am Zick: Improving The Efficiency and Reliability Of On-Board Processing via Physically-Adaptive Computing

11:30 am - 1:00 pm Lunch

Track 2 - MAPLD

7:30 am - 8:30 am Breakfast

Session D

8:30 am - 8:50 am Habinc: Implementing SpaceWire Routers As Standard Products Using FPGA Technology

8:50 am - 9:10 am Ostler: Dynamic Partial Reconfiguration Of Softcore Processors On The Virtex 5

9:10 am - 9:30 am
Mohsen: FPGA SynthesisBased Radiation Effects Mitigation Using Triple Modular Redundancy And Safe FSM Implementations

9:30 am - 9:50 am Walters: Radiation Hardening By Software For The Embedded PowerPC, Preliminary Findings

9:50 am - 10:10 am Nguyen: Actel RTAX-DSP Design Techniques For High Reliability Application

10:10 am - 10:30 am Break

10:30 am - 10:50 am Fitch: Applying Modern Verification Methods To VHDL Designs

10:50 am - 11:10 am Wang: Design Choices And Guidelines For Configuration Monitoring And Management Of The RHBD Virtex-5QV Space-grade FPGA

11:10 am - 11:30 am Swift: Prototyping V-5QV Space Applications Using The Commercial-Grade FPGAs And Boards

11:30 am - 11:50 am Ginosar: A Design Flow For FPGA Conversion Into Radiation-Hardened ASIC

11:50 am - 1:00 pm Lunch