Conference Schedule

Tuesday, November 2, 2010

Track 1 - ReSpace and Track 2 - MAPLD

Session - Plenary
7:00 am	Breakfast
8:00 am - 8:15 am	Suddarth: Opening Remarks
8:15 am - 8:45 am	Abbot: History Of Surrey
8:45 am - 9:15 am	Puig-Suari: History Of Cube Sats
9:15 am - 9:45 am	Nixon:Small Sats, Electronics and "Wicked" Problems
9:45 am - 10:15 am	Break
10:15 am - 10:30 am	Powell: NASA Opening Remarks
10:30 am - 11:00 am	Troxel: Trends In Reconfigurable And High Performance Electronics For Space
11:00 am - 11:30 am	Lyke: Space Plug-and-play Avionics (SPA)
11:30 am - 12:15 pm	Break
12:15 pm	Lunch and Panel Session (Are You Crazy Flying That?)-Panel Moderator: Ken LaBel, NASA

Track 1 - ReSpace

Session I - SPA Standardization
1:30 pm - 2:00 pm	Howe: Kit Of Parts Architecture
2:00 pm - 2:30 pm	Hansen / Graven: GNC Hierarchy Using SPA
2:30 pm - 3:00 pm	Christensen / Cannon: SPA Network Management
3:00 pm - 3:30 pm	Break
3:30 pm - 4:00 pm	Schenk: Advanced Plug - n - Play Technologies (APT) Lessons Learned
4:00 pm - 5:30 pm	Making SPA Work: Industry Input, the Standards Process, and Where we are Now - Panel Chair: Millay Morgan, APT
6:15 pm	Dinner - "Meet The Experts"

Track 2 - MAPLD

Session A - Mil / Aero Market Update For FPGAs And Associated Devices
1:30 pm - 1:40 pm	Ward: Non-Volatile And Volatile Carbon Nanotube Electronics For Reconfigurable, Radiation Hard Space Based Applications
1:40 pm - 1:50 pm	Wang: Very High Density and Radiation Tolerant PROM For Space Syatems
1:50 pm - 2:00 pm	Philpy: 90nm Design-Hardened Structured ASIC; The Next Generation of Digital ICs for Space
2:00 pm - 2:10 pm	Wolday: Actel's RTAX4000D Space Qualification Update
2:10 pm - 2:20 pm	Katzman: Space Qualified Ultra-High Speed Plug-and Play Radiation Hard SERDES
2:20 pm - 2:30 pm	Lake: Aeroflex Non-Volatile Boot Memory For Xilinx FPGAs
2:30 pm - 2:40 pm	Swonger: Radiation Hardened Integrated Point-of-load DC-DC Converter On Sapphire
2:40 pm - 2:50 pm	Puchner: High Speed Radiation Hard 72Mbit Quad Data Rate SRAM For Space Applications
2:50 pm - 3:00 pm	Carmichael: Introducing The Virtex-5QV Reconfigurable FPGA: The Biggest And Fastest Space-grade Part On The Planet
3:00 pm - 3:30 pm	Break
3:30 pm - 3:40 pm	Ginosar: JPIC - Rad-Hard JPEG2000 Image Compression ASIC
3:40 pm - 3:50 pm	Bancelin: ATMEL ATF280F Rad Hard SRAM Based Dynamic Partial Reconfiguration
3:50 pm - 4:00 pm	Jones: The Advantages And Challenges Of Using Many-core Processors For Space-based Applications
4:00 pm - 4:10 pm	Elftmann: RadRunner
Session B -Flight / Field Plans And Experiences With FPGAs And PLDs
4:10 pm - 4:30 pm	Hodson: LIDAR Image processing acceleration via FPGA implementation
4:30 pm - 4:50 pm	Espinosa: SpaceCube On-Board Science Data Processor: Current Applications and Future Architectures
4:50 pm - 5:10 pm	Morgan: LANL Cube Sat Reconfigurable Computer (CRC)
5:10 pm - 5:30 pm	Howard: Highly Scalable/Highly Configurable FPGA Based Solid State Recorder For Multi-Mission Space Applications
6:15 pm	Dinner - "Meet The Experts"