LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS 

  -- Component Declaration
          COMPONENT debounce
          PORT(
				clk					:	in	std_logic;
				switch_input		:	in	std_logic;
				debounced_output	:	out	std_logic
				);
          END COMPONENT;

		SIGNAL clk 	: std_logic := '0';
		SIGNAL switch_input : std_logic := '0';
		SIGNAL debounced_output : std_logic := '0';
--UUT means unit under test
BEGIN
UUT : debounce

--map signals on right to entitys on the left
	PORT MAP (
	clk => clk,
	switch_input => switch_input,
	debounced_output => debounced_output
	);

signal_clk: process
begin
	clk <= NOT clk;
	wait for 1 ns;
end process;

signal_switch_input: process
begin
	switch_input <= '0';
	wait for 15 ns;
	switch_input <= '1';
	wait for 2 ns;
	switch_input <= '0';
	wait for 1000000 ns;
end process;

  END;